Fix ASSERT failure caused by NX support code on x86_64

When turning on debug for x86_64, ASSERT(gpfn =3D=3D (gpfn & =
PGT_mfn_mask))
in __shadow_status will fail, this patch makes the NX support code
comply with this ASSERT.
NB: NX on PAE xen is not supported yet.

Signed-off-by: Xin Li <xin.b.li@intel.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>

diff --git a/xen/arch/x86/shadow.c b/xen/arch/x86/shadow.c
index f63dc667ea963c4490f753ceb25bad75b3616fc6..1f312a4fdbb109026a1fc422203caec34233edc4 100644 (file)
--- a/xen/arch/x86/shadow.c
+++ b/xen/arch/x86/shadow.c
@@ -3413,7 +3413,9 @@ static inline int l2e_rw_fault(
     l1_pgentry_t sl1e;
     l1_pgentry_t old_sl1e;
     l2_pgentry_t sl2e;
+#ifdef __x86_64__
     u64 nx = 0;
+#endif
     int put_ref_check = 0;
     /* Check if gpfn is 2M aligned */
 
@@ -3428,7 +3430,9 @@ static inline int l2e_rw_fault(
     l2e_remove_flags(tmp_l2e, _PAGE_PSE);
     if (l2e_get_flags(gl2e) & _PAGE_NX) {
         l2e_remove_flags(tmp_l2e, _PAGE_NX);
-        nx = 1ULL << 63;
+#ifdef __x86_64__
+        nx = PGT_high_mfn_nx;
+#endif
     }
 
 
@@ -3436,7 +3440,11 @@ static inline int l2e_rw_fault(
     if ( !__shadow_get_l2e(v, va, &sl2e) )
         sl2e = l2e_empty();
 
+#ifdef __x86_64__
     l1_mfn = __shadow_status(d, start_gpfn | nx, PGT_fl1_shadow);
+#else
+    l1_mfn = __shadow_status(d, start_gpfn, PGT_fl1_shadow);
+#endif
 
     /* Check the corresponding l2e */
     if (l1_mfn) {
@@ -3454,7 +3462,11 @@ static inline int l2e_rw_fault(
     } else {
         /* Allocate a new page as shadow page table if need */
         gmfn = gmfn_to_mfn(d, start_gpfn);
+#ifdef __x86_64__
         l1_mfn = alloc_shadow_page(d, start_gpfn | nx, gmfn, PGT_fl1_shadow);
+#else
+        l1_mfn = alloc_shadow_page(d, start_gpfn, gmfn, PGT_fl1_shadow);
+#endif
         if (unlikely(!l1_mfn)) {
             BUG();
         }

diff --git a/xen/include/asm-x86/mm.h b/xen/include/asm-x86/mm.h
index 8cfe942e8e202cc882106b76220f22e59ad0305b..3e218d1decec065742117218230c189dbc1946cf 100644 (file)
--- a/xen/include/asm-x86/mm.h
+++ b/xen/include/asm-x86/mm.h
@@ -98,8 +98,17 @@ struct page_info
  /* 16-bit count of uses of this frame as its current type. */
 #define PGT_count_mask      ((1U<<16)-1)
 
+#ifdef __x86_64__
+#define PGT_high_mfn_shift  52
+#define PGT_high_mfn_mask   (0x7ffUL << PGT_high_mfn_shift)
+#define PGT_mfn_mask        (((1U<<23)-1) | PGT_high_mfn_mask)
+#define PGT_high_mfn_nx     (0x800UL << PGT_high_mfn_shift)
+#else
  /* 23-bit mfn mask for shadow types: good for up to 32GB RAM. */
 #define PGT_mfn_mask        ((1U<<23)-1)
+ /* NX for PAE xen is not supported yet */
+#define PGT_high_mfn_nx     (1ULL << 63)
+#endif
 
 #define PGT_score_shift     23
 #define PGT_score_mask      (((1U<<4)-1)<<PGT_score_shift)